A well-known problem with integrated circuit capacitors is that their capacitance does not scale directly with drawn area. The capacitance at the edge will be affected by linewidth variations, and also by fringing field effects. This is not a problem for very small arrays, but becomes more of a problem as the number of capacitors in the array increases. Thus if we try to build a chain of 8 capacitors scaled by powers of two, we may find that the transition from 01111111 to 1000000 is in the wrong direction, or is excessively large.
MOS capacitors provide a fairly high raw capacitance per unit area, but the capacitance of MOS capacitors is affected by a number of process parameters, e.g., gate oxide thickness, substrate doping, well doping if used, VT doping if used, linewidth variation (in polysilicon and in active), and variations in the degree of birds beak encroachment on the active area, (and hence variation in the capacitance of a capacitor whose area is determined by an active area pattern). Moreover, variations in field oxidation conditions and/or channel stop implant may produce some variation in the doping underlying the birds beak extension, and this too will have some effect on the capacitance contribution at the perimeter of a MOS capacitor.
This is particularly a problem in converters (ADCs and DACs), where capacitor ladders are very commonly used. However, similar problems may arise in many other analog circuit contexts. Accurate capacitor ladders provide digitally selectable reactances which can be useful for various telecommunications, radio frequency, and switched-capacitor circuits.
Many attempts have been made to compensate for this problem. For example, U.S. Pat. No. 5,579,005, which is hereby incorporated by reference, describes an innovative way to correct for capacitor nonlinearity; but the present application proposes a hardware technique to effectively eliminate it.
There is a need for an integrated circuit capacitor array structure that provides accurate capacitance values by compensating for edge effects and variations in the areas of individual capacitors in the array.